COURSE TAUGHT RECENTLY

EE7510 - Digital Wideband Receiver Design

EE7520 - Low Power VLSI System Design

EE7530 - VLSI Design Synthesis and Optimization

EE7540 - VLSI Testing and Design for Testability

EE4620 - Digital Integrated Circuit Design with PLDs and FPGAs

EE4540 - VLSI Design

EE3310 - Electronic Devices and Circuits

EE2000 - Digital Design with VHDL

RESEARCH AREA

VLSI/FPGA design and test, spanning digital designs and RF components and extending to embedded system applications, such as radar and ultra-wideband digital receivers, and assured hardware security.

Selected papers:

1. Jayarama, K. and Chen, C.-I. H., "Dual-Channel Multi-Frame FFT Processing for Precise Multi-Signal Detection in Closed-Space RF Environments," IEEE Transactions on Instrumentation and Measurement, Vol. 74, pp. 1-14, 2025.
2. Abdulhamed, B. and Chen, C.-I. H., “High Sensitivity Digital Instantaneous Frequency Measurement Receiver for Precise Frequency Analysis,” Journal of Computer and Communications, Vol. 12. No. 1, pp. 177-190, Jan., 2024.
3. Jayarama, K. and Chen, C.-I. H., “Enhanced Wideband Frequency Estimation via FFT: Leveraging Polynomial Interpolation and Array Indexing,” Journal of Computer and Communications, Vol. 12. No. 1, pp. 35-48, Jan., 2024.
4. Wang, Y., Ren, J. and Chen, C.-I. H., “Calibration of Optimized Minimum Inductor Bandpass Filter with Controllable Bandwidth and Stopband Rejection,” Integration, the VLSI Journal, Vol. 81, pp. 300-321, July 2021.
5. Allwin, P. S. and Chen, C.-I. H., “A Low-Area, Low-Power Dynamically Reconfigurable 64-bit Media Signal Processing Adder,” Journal of Computer and Communications, Vol. 9, No. 3, pp. 54-69, March 2021.
6. Liu, F. and Chen, C.-I. H., “High Two-Signal Dynamic Range and Accurate Frequency Measurement for Close Frequency Separation Wideband Digital Receiver Using Adaptive Gain Control and Dynamic Thresholding,” Integration, The VLSI Journal, Vol. 72, pp. 72-81, May 2020.
7. Wang, Y., Chen, J. and Chen, C.-I. H., “Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor, VLSI Design, Vol. 2017, Article ID 5369167, 12 pages, 2017. 
8. Lin, E., Chen, C.-I. H., Liou, L. L. and Lin, D. M., “Performance Analysis of Digital Wideband Receiver based on Reconstruction of Compressive Sensing Data,” IEEE Radar Conference, pp. 0830-0835, Seattle, WA, May 2017.
9. Benson, S. and Chen, C.-I. H., Lin, M. D. and Liou, L. L., “High Linear Chirp Receiver Using High Resolution Time-of-Arrival Estimation,” IEEE Transactions on Aerospace and Electronic Systems, 2016. Vol. 52, No. 3. pp. 1146-1154, June 2016.
10. Xue, H. and Chen, C.-I. H., “Timing and Power Optimization Using Mixed-Dynamic-Static CMOS,” International Journal of Emerging Technology and Advanced Engineering, Vol. 6, No. 3, pp.  19-28, November 2016. 
11. Lin, E., Chen, C.-I. H., Liou, L. L. and Lin, D. M., “Detection and Sensitivity Analysis of Compressed Sensing Electronic RF Receiver,” IEEE Radar Conference, pp. 1-6, Philadelphia PA, May 2016.
12. Chen, J. and Chen, C.-I. H., “Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection,” VLSI Design, Vol. 2015, Article ID 408035,, pp. 1-9, 2015.
13. George, K. and Chen, C.-I. H., “Performance Measurement of a High-Performance Computing System Utilized for Electronic Medical Record Management,” International Journal of Advancements in Computing Technology, Vol. 7, No. 1, pp. 1-8, January 2015.
14. Chen, J. and Chen, C.-I. H, “1-2 GHz Tuning Frequency Band Pass Filter with Controllable Pass Band and High Stopband Rejection, IEEE International Microwave Symposium, pp. 1-4, Phoenix, AZ, May 2015.
15. George, K. and Chen, C.-I. H., “Multiple Signal Detection Digital Wideband Receiver Utilizing Hardware Accelerators,” IEEE Transactions on Aerospace and Electronic Systems, Vol. 49, No. 2, pp. 706-715, April 2013.
16. George, K. and Chen, C.-I. H., “Measurement Setup and Performance Analysis of Digital Receiver System with Multiple Signal Detection and Expandable Bandwidth Capabilities on a Multi-Processor Hardware Platform,” International Journal of Engineering Sci. and Man., Vol. 3, No. 1, pp. 46-54, 2013.
17. Yelamarthi, Y. and Chen, C.-I. H., “Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations,” IEEE Transactions on Semiconductor Manufacturing, Vol. 25, No. 2, pp. 255-265, May 2012.
18. George, K. and Chen, C.-I. H., “A Hybrid Computing Platform Digital Wideband Receiver Design Instrumentation and Performance Measurement,” IEEE Transactions on Instrumentation and Measurement, Vol. 60, No. 12, pp. 3956-3958, Dec. 2011.
19. George, K. and Chen, C.-I. H., “Biologically-Inspired Signal Processor Using Lateral Inhibition and Integrative Function Mechanisms for High Instantaneous Dynamic Range,” International Journal on Smart Sensing and Intelligent Systems, Vol. 4, No. 4, pp. 547-567, Dec. 2011.
20. Benson, S. and Chen, C.-I. H., “Adaptive Thresholding for High Dual-Tone Signal Instantaneous Dynamic Range in Digital Wideband Receiver,” IEEE Transactions on Instrumentation and Measurement, Vol. 60, No. 5, pp. 1869-1875, May 2011.
21. Yelamarthi, Y. and Chen, C.-I. H., “Dynamic CMOS Load Balancing and Path Oriented In Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations,” VLSI Design, Vol. 2010, Article ID 230783, pp. 1-13, 2010.
22. Lee, Y.-H. G. and Chen, C.-I. H., “Dynamic Kernel Function Fast Fourier Transform with Variable Truncation Scheme for Wideband Coarse Frequency Detection,” IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 5, pp. 1495-1504, May 2009.
23. George, K. and Chen, C.-I. H., “Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip,” IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 5, pp. 1555-1562, May 2009.
24. Yelamarthi, Y. and Chen, C.-I. H., “Process-Variation Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic,” IEEE Transactions on Semiconductor Manufacturing, Vol. 22, No, 1, pp. 31-39, 2009. 
25. Yelamarthi, Y. and Chen, C.-I. H., “Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization,” Journal of Computers, Academy Publisher, Vol. 3, No. 2, pp. 21-28, Feb. 2008.
26. Wibbenmeyer, J. and Chen, C.-I. H., “Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters,” IEEE Transactions on Instrumentation and Measurement, Vol. 56, No. 6, pp. 2748-2756, Dec. 2007.
27. Wang, M.; Chen, C.-I. H. and Radhakrishnan, S, “Low-Power 4-b 2.5 GSPS Pipelined Flash Analog-to-Digital Converters in 130-nm CMOS,” IEEE Transactions on Instrumentation and Measurement, Vol. 56, No. 3, pp. 1064-1073, June 2007.
28. George, K.; Chen, C.-I. H., and Tsui, J. B.-Y., “Extension of Two-Signal Spurious-Free Dynamic Range of Wideband Digital Receiver using Kaiser Window and Compensation Method,” IEEE Transactions on Microwave Theory and Techniques, Vol. 55, No. 4, pp. 788-794, April 2007. 
29. Chen, C.-I. H.; George, K.; McCormick W; Tsui, J. B. Y.; Hary S. and Graves K., “Design and Performance Evaluation of 2.5 GSPS Digital Receiver,” IEEE Transactions on Instrumentation and Measurement, Vol. 54, No. 3, pp. 1089-1099, June 2005. 
30. Chen, C.-I. H. and George, K., “Configurable Two-dimensional Linear Feedback Shifter Registers for Parallel and Serial Built-In Self-Test,” IEEE Transactions on Instrumentation and Measurement, Vol. 53, No. 4, pp. 1005-1014, August 2004.

Ph.D Dissertation Supervised

Continuing Students:

Bilal Abdulhamed                      Deep Learning for Signal Detection and Classification in Chirp Signals (date passed Ph.D. Candidacy Exam: Spring 2023)

Lakshmi Ronanki                      Beyond Register Transfer Level: Machine Learning for Predictive and Scalable Digital Design Synthesis (date passed Ph.D. Candidacy Exam: Spring 2024)

Graduated Students:

Kiran Jayarama                         High Two-Signal Dynamic Range Digital Wideband Receiver for Multiple Signal Detection: Theory, Design, and System Integration, Fall 2025 (initial employer:                                                          Synopsys, Boxborough, MA)

Jianfeng Ren                            CMOS Wide Tuning Inductor/Inductorless Gilbert Mixer with Controllable Bandwidth for Multi-Band/Multi-Standard Applications in Upcoming RF Frontends,                                                               Fall 2023 (initial employer: China Southern Power Grid, Guangzhou, China)

Yu Wang                                  Design and Implementation of Fully Integrated CMOS On-chip Bandpass Filter with Wideband High-Gain Low Noise Amplifier, Summer 2021 (initial employer:                                                        Qualcomm, San Diego, CA)

Jian Chen                                 RF CMOS Band Pass Filters with Wide Tuning Frequency, Controllable Pass Band and High Stopband Rejection: Using Passive and Active Inductors, Fall 2016                                                     (initial employer: Assistant Professor, Dongguan University of Technology, Donguan, China)

Ethan Lin                                  Compressed Sensing for Electronic Radio Frequency Receiver: Detection, Sensitivity, and Implementation, Dec. 2015 (AFRL/RYWE, WPAFB, Dayton, OH)

Stephen Benson                       Modern Digital Chirp Receiver: Theory, Design and System Integration, Dec. 2015 (Raytheon, Tucson, AZ)

George Y.-H. Lee                      Dynamic Kernel Function Fast Fourier Transform Variable Truncation Error Analysis and Performance Evaluation, Dec. 2009 (Northrop Grumman, Dayton, OH;                                                       General Dynamics Mission Systems, Scottsdale, AZ)

Kumar Yelamarthi                     Process Variation Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic, June 2008                                                                             (Full Professor of Electrical Engineering, Central Michigan University, MI; Dean of College of CECS, The University of Tennessee, TN)

Mingzhen Wang                        High-Speed Low-Power Pipelined Flash A/D Converter for System-on-a-Chip Applications, Dec. 2007 (initial employer: Assistant Professor of Electronic                                                                    Engineering Department at University of Electronic Science and Technology of China, Chengdu, China)

Kiran George                             Design and Performance Evaluation of 1 Giga Hertz Wideband Digital Receiver, Sept. 2007 (Associate Dean of College of Engineering and Computer Science                                                         and Full Professor of Computer Engineering, California State University, Fullerton, CA)

Editorial Board                                                                                              

Integration, the VLSI Journal                                                                                 Associate Editor (2010-present)

Chips                                                                                                                         Editorial Board Member (2024-present)

Journal of Electrical and Computer Engineering                                                Editorial Board Member (2018-present)

2023–2024 Wright State University Trustees’ Award for Faculty Excellence

2019 Wright State University, College of Engineering and Computer Science, Faculty Excellence in Outstanding Award

2016 IEEE Harrell V. Noble Award (Dayton Section)

1995 Wright State University, College of Engineering and Computer Science, Faculty Excellence in Research Award