Henry Chen

Department:
Electrical Engineering
Title:
Professor of Electrical Engineering
Address:
Russ Engineering Center 325, 3640 Colonel Glenn Hwy., Dayton, OH 45435-0001
Phone:
937-775-5056
Email:
henry.chen@wright.edu

Professor Henry Chen received his Ph.D. degree in electrical engineering from the University of Minnesota, Minneapolis. Since joining Wright State University, he has worked primarily in VLSI/FPGA, spanning digital designs and RF components and extending to embedded system applications, such as radar and ultra-wideband digital receivers, and assured/trusted hardware security, where he is currently a Professor. Professor Chen collaborates with researchers from various disciplines to advance the development of ultra-wideband receivers for efficiently collecting, analyzing, and classifying signals in the noisy signal environment within a wide radio-frequency spectrum. Professor Chen received the 2016 IEEE Harrell V. Noble Award, Dayton Section, “For the development of wideband receiver technology capable of detecting high chirp rate signals and realizing this state-of-the-art receiver technology in a real-time hardware prototype.” Professor Chen’s foundational contributions to his primary field of research are derived from problems posed by the wide variety of possible application areas. He has supervised 13 doctoral and 50 master students on application topics and has published over 45 Journal articles alongside 81 conference papers. He has served on technical committees at numerical IEEE conferences. He is currently on the Editorial Board of journals such as Chips, Integration – the VLSI, and Journal of Electrical and Computer Engineering. He has consulted for several US semiconductor companies.

Curriculum Vitae

Henry Chen CV.pdf 272.23 KB

Teaching

COURSE TAUGHT RECENTLY

EE7510 - Digital Wideband Receiver Design

EE7520 - Low Power VLSI System Design

EE7530 - VLSI Design Synthesis and Optimization

EE7540 - VLSI Testing and Design for Testability

EE4620 - Digital Integrated Circuit Design with PLDs and FPGAs

EE4540 - VLSI Design

EE3310 - Electronic Devices and Circuits

EE2000 - Digital Design with VHDL

EE8000 - Mixed Signal Tools

Research Statement

RESEARCH AREA

VLSI/FPGA design, spanning digital designs and RF components and extending to embedded system applications, such as radar and ultra-wideband digital receivers, and assured/trusted hardware security.

Publications

Selected papers:

  1. Abdulhamed, B. and Chen, C.-I. H., “High Sensitivity Digital Instantaneous Frequency Measurement Receiver for Precise Frequency Analysis,” Journal of Computer and Communications, Vol. 12. No. 1, pp. 177-190, Jan., 2024.
  2. Jayarama, K. and Chen, C.-I. H., “Enhanced Wideband Frequency Estimation via FFT: Leveraging Polynomial Interpolation and Array Indexing,” Journal of Computer and Communications, Vol. 12. No. 1, pp. 35-48, Jan., 2024.
  3. Wang, Y., Ren, J. and Chen, C.-I. H., “Calibration of Optimized Minimum Inductor Bandpass Filter with Controllable Bandwidth and Stopband Rejection,” Integration, the VLSI Journal, Vol. 81, pp. 300-321, July 2021.
  4. Allwin, P. S. and Chen, C.-I. H., “A Low-Area, Low-Power Dynamically Reconfigurable 64-bit Media Signal Processing Adder,” Journal of Computer and Communications, Vol. 9, No. 3, pp. 54-69, March 2021.
  5. Liu, F. and Chen, C.-I. H., “High Two-Signal Dynamic Range and Accurate Frequency Measurement for Close Frequency Separation Wideband Digital Receiver Using Adaptive Gain Control and Dynamic Thresholding,” Integration, The VLSI Journal, Vol. 72, pp. 72-81, May 2020.
  6. Wang, Y., Chen, J. and Chen, C.-I. H., “Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor, VLSI Design, Vol. 2017, Article ID 5369167, 12 pages, 2017. 
  7. Lin, E., Chen, C.-I. H., Liou, L. L. and Lin, D. M., “Performance Analysis of Digital Wideband Receiver based on Reconstruction of Compressive Sensing Data,” IEEE Radar Conference, pp. 0830-0835, Seattle, WA, May 2017.
  8. Benson, S. and Chen, C.-I. H., Lin, M. D. and Liou, L. L., “High Linear Chirp Receiver Using High Resolution Time-of-Arrival Estimation,” IEEE Transactions on Aerospace and Electronic Systems, 2016. Vol. 52, No. 3. pp. 1146-1154, June 2016.
  9. Xue, H. and Chen, C.-I. H., “Timing and Power Optimization Using Mixed-Dynamic-Static CMOS,” International Journal of Emerging Technology and Advanced Engineering, Vol. 6, No. 3, pp.  19-28, November 2016. 
  10. Lin, E., Chen, C.-I. H., Liou, L. L. and Lin, D. M., “Detection and Sensitivity Analysis of Compressed Sensing Electronic RF Receiver,” IEEE Radar Conference, pp. 1-6, Philadelphia PA, May 2016.
  11. Chen, J. and Chen, C.-I. H., “Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection,” VLSI Design, Vol. 2015, Article ID 408035,, pp. 1-9, 2015.
  12. George, K. and Chen, C.-I. H., “Performance Measurement of a High-Performance Computing System Utilized for Electronic Medical Record Management,” International Journal of Advancements in Computing Technology, Vol. 7, No. 1, pp. 1-8, January 2015.
  13. Chen, J. and Chen, C.-I. H, “1-2 GHz Tuning Frequency Band Pass Filter with Controllable Pass Band and High Stopband Rejection, IEEE International Microwave Symposium, pp. 1-4, Phoenix, AZ, May 2015.
  14. George, K. and Chen, C.-I. H., “Multiple Signal Detection Digital Wideband Receiver Utilizing Hardware Accelerators,” IEEE Transactions on Aerospace and Electronic Systems, Vol. 49, No. 2, pp. 706-715, April 2013.
  15. George, K. and Chen, C.-I. H., “Measurement Setup and Performance Analysis of Digital Receiver System with Multiple Signal Detection and Expandable Bandwidth Capabilities on a Multi-Processor Hardware Platform,” International Journal of Engineering Sci. and Man., Vol. 3, No. 1, pp. 46-54, 2013.
  16. Yelamarthi, Y. and Chen, C.-I. H., “Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations,” IEEE Transactions on Semiconductor Manufacturing, Vol. 25, No. 2, pp. 255-265, May 2012.
  17. George, K. and Chen, C.-I. H., “A Hybrid Computing Platform Digital Wideband Receiver Design Instrumentation and Performance Measurement,” IEEE Transactions on Instrumentation and Measurement, Vol. 60, No. 12, pp. 3956-3958, Dec. 2011.
  18. George, K. and Chen, C.-I. H., “Biologically-Inspired Signal Processor Using Lateral Inhibition and Integrative Function Mechanisms for High Instantaneous Dynamic Range,” International Journal on Smart Sensing and Intelligent Systems, Vol. 4, No. 4, pp. 547-567, Dec. 2011.
  19. Benson, S. and Chen, C.-I. H., “Adaptive Thresholding for High Dual-Tone Signal Instantaneous Dynamic Range in Digital Wideband Receiver,” IEEE Transactions on Instrumentation and Measurement, Vol. 60, No. 5, pp. 1869-1875, May 2011.
  20. Yelamarthi, Y. and Chen, C.-I. H., “Dynamic CMOS Load Balancing and Path Oriented In Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations,” VLSI Design, Vol. 2010, Article ID 230783, pp. 1-13, 2010.
  21. Lee, Y.-H. G. and Chen, C.-I. H., “Dynamic Kernel Function Fast Fourier Transform with Variable Truncation Scheme for Wideband Coarse Frequency Detection,” IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 5, pp. 1495-1504, May 2009.
  22. George, K. and Chen, C.-I. H., “Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip,” IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 5, pp. 1555-1562, May 2009.
  23. Yelamarthi, Y. and Chen, C.-I. H., “Process-Variation Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic,” IEEE Transactions on Semiconductor Manufacturing, Vol. 22, No, 1, pp. 31-39, 2009. 
  24. Yelamarthi, Y. and Chen, C.-I. H., “Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization,” Journal of Computers, Academy Publisher, Vol. 3, No. 2, pp. 21-28, Feb. 2008.
  25. Wibbenmeyer, J. and Chen, C.-I. H., “Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters,” IEEE Transactions on Instrumentation and Measurement, Vol. 56, No. 6, pp. 2748-2756, Dec. 2007.
  26. Wang, M.; Chen, C.-I. H. and Radhakrishnan, S, “Low-Power 4-b 2.5 GSPS Pipelined Flash Analog-to-Digital Converters in 130-nm CMOS,” IEEE Transactions on Instrumentation and Measurement, Vol. 56, No. 3, pp. 1064-1073, June 2007.
  27. George, K.; Chen, C.-I. H., and Tsui, J. B.-Y., “Extension of Two-Signal Spurious-Free Dynamic Range of Wideband Digital Receiver using Kaiser Window and Compensation Method,” IEEE Transactions on Microwave Theory and Techniques, Vol. 55, No. 4, pp. 788-794, April 2007. 
  28. Chen, C.-I. H.; George, K.; McCormick W; Tsui, J. B. Y.; Hary S. and Graves K., “Design and Performance Evaluation of 2.5 GSPS Digital Receiver,” IEEE Transactions on Instrumentation and Measurement, Vol. 54, No. 3, pp. 1089-1099, June 2005. 
  29. Chen, C.-I. H. and George, K., “Configurable Two-dimensional Linear Feedback Shifter Registers for Parallel and Serial Built-In Self-Test,” IEEE Transactions on Instrumentation and Measurement, Vol. 53, No. 4, pp. 1005-1014, August 2004.

Professional Affiliations/Memberships

Editorial Board                                                                                              

Integration, the VLSI Journal                                                                                 Associate Editor (2010-present)

Chips                                                                                                                         Editorial Board Member (2024-present)

Journal of Electrical and Computer Engineering                                                Editorial Board Member (2018-present)

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