Henry Chen

Department:
Electrical Engineering
Title:
Professor of Electrical Engineering
Address:
Russ Engineering Center 325, 3640 Colonel Glenn Hwy., Dayton, OH 45435-0001
Phone:
937-775-5056

Professor Henry Chen received his Ph.D. degree from the University of Minnesota, Minneapolis, in 1989, in electrical engineering. Since joining Wright State University in 1989 he has worked primarily in the area of digital and mixed-signal integrated circuits, VLSI/FPGA/GPU for signal processing, communication and ultra wideband receivers, where he is currently a Professor.  Professor Chen collaborates with researchers from a range of disciplines to advance the development of ultra wideband receivers for efficiently collecting, analyzing and classifying signals in noisy signal environment within a wide radio-frequency spectrum. 

Academics

COURSE TAUGHT RECENTLY

EE7520 - Low Power VLSI System Design

EE7540 - VLSI Testing and Design for Testability

EE4540 - VLSI Design

EE3310 - Electronic Devices and Circuits

EE2000 - Digital Design with VHDL

EE8000 - Mixed Signal Tools

Research statement: 

RESEARCH AREA

Digital and mixed-signal integrated circuits, VLSI/FPGA/GPU for signal processing, communication and ultra wideband receivers.   

Domains   -   Electronic warfare, cyber security, VLSI, FPGA, GPU.

Students Advised: 

Ph.D. DISSERTATION SUPERVISED

Continuing Students

Kaushik Katpally, Feiran Liu, Jian-Feng Ren, Jian Chen, Prasanna Daram

Graduated Students

Ethan Lin                                 Compressed Sensing for Electronic Radio Frequency Receiver: Detection, Sensitivity, and Implementation, Dec. 2015 (initial employer: UDRI, Dayton, OH).

Stephen Benson                      Modern Digital Chirp Receiver: Theory, Design and System Integration, Dec. 2015 (initial employer: Edaptive Computing Inc., Dayton, OH).

George Y.-H. Lee                     Dynamic Kernel Function Fast Fourier Transform Variable Truncation Error Analysis and Performance Evaluation, Dec. 2009 (initial employer: Research Scientist, Wright   State University, Dayton, OH).

Kumar Yelamarthi                   Process Variation Aware Timing Optimization with Load Balance of Multiple Paths in Dynamic and Mixed-Static-Dynamic CMOS Logic, June 2008 (initial employer: Assistant Professor of Electrical Engineering, Central Michigan University, Mount Pleasant, MI).

Mingzhen Wang                      High-Speed Low-Power Pipelined Flash A/D Converter for System-on-a-Chip Applications, Dec. 2007 (initial employer: Assistant Professor of Electronic Engineering Department at University of Electronic Science and Technology of China, Chengdu, China).

Kiran George                           Design and Performance Evaluation of 1 Giga Hertz Wideband Digital Receiver, Sept. 2007 (initial employer: Assistant Professor of Computer Engineering, California State University, Fullerton, CA).

M.S. THESES SUPERVISED
Continued Students
Yu Wang, Lihzong He, Xin Hu

Graduated Students

Feiran Liu                                High Resolution and Dynamic Range Adaptive Thresholding Wideband Digital Receiver, Dec. 2015 (Ph.D at Wright State University)

Julin Sha                                 Compressive Sensing Analog Front-End Design in 180 nm CMOS Technology, Summer 2015. (initial employer: Nishtech, Cincinnati, OH)

Surya Kiran Akkaladevi            Design and Performance Analysis of Magnetic Adder and 16-Bit MRAM Using Magnetic Tunnel Junction Transistor, Spring 2015.

Linda Chu                                Adaptive I/Q Mismatch Compensation for Wideband Receiver, fall 2014 (initial employer: Riverside Research, Dayton, OH).

Kaushik Katpally                      Dynamic Repeater with Booster Enhancement for Fast Switching Speed and Propagation in Long Interconnect, fall 2014 (Ph.D at Wright State University).

Hao Xue                                  Timing and Power Optimization for Mixed-Dynamic-Static CMOS, summer 2013 (Ph.D at Wright State University).

Duo Zhang                               Dynamic CMOS MIMO Circuits with Feedback Inverter Loop and Pull-Down Bridge, summer 2013.

Ramadan Buzukuk                   Dynamic Footed with Clock Overlapping and Load Balancing in Multiple Paths for Noise Tolerance in Dynamic CMOS Circuits, fall 2011 (initial employer: Qualcomm, San Diego, CA).

A. Vaidyanadeswaran              Circuit Techniques on Improving Timing and Noise in Dynamic CMOS, winter 2011 (initial employer: Intel, Folsom, CA).

Stephen Benson                      Adaptive Thresholding for Detection of Radar Receiver Signals, summer 2010 (continueing Ph.D at Wright State University).

Dilip S. Murthy                         Real-Time Hilbert Transform and Auto-correlation for Digital Instantaneous Frequency Measurement Receiver, fall 2008 (initial employer: IBM India Pvt Ltd, India).

Ryan Bone                               FPGA-Based Low-Power 256-point FFT Processor, estimated summer 2008 (initial employer: Science Applications International Corporation (SAIC), Beavercreek, OH).

Vivek Sarathy                           High Spurious-Free Dynamic Range Digital Wideband Receiver for Multiple Signal Detection/Tracking, fall 2007 (initial employer: QuStream Corportion, Huntsville, AL).

Rajasekhar Keerthi                   Stability and Static Noise Margin Analysis of Static Random Access Memory, fall 2007.                  

James Helton                           FPGA-Based Processor for Digital Instantaneous Frequency Measurement (IFM) Receiver, summer 2007 (initial employer: Science Applications International Corporation (SAIC), Beavercreek, OH).

Brian Poling                            On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In Self-Test of General Receiver Systems, summer 2007 (WPAFB, Dayton, OH).

Tony Chiang                            Design and Performance Evaluation of a Discrete Wavelet Transform Based Multi-Signal Receiver, spring 2006 (initial employer: Daetwyler Corp., Dayton, OH).

Cyprian Sajabi                         FPGA Frequency Domain Based GPS Code Acquisition Processor Using FFT, spring 2006 (initial employer: Nova Systems Solutions, Cincinnati, OH).

Siaw-Yuen Ng                          Automated Generation, Optimization and Synthesis of 2-Dimensional Linear Feedback Shift Registers Framework for Built-In Self-Test, spring 2006 (initial employer: Jiin & Associates Co. Ltd., Segamat, Johor, Malaysia).

Sashank Kakulavarapu             High Speed Signed Multiplier Using Baugh-Wooley & On-The-Fly Conversion Algorithms, winter 2005 (initial employer: Harvard Pilgrim, Boston, MA).

Vivek Chandrasekhar                Low-Cost Low-Power Self-Test Design and Verification for On-chip ADC in System-on-a-Chip Applications, winter 2005 (initial employer: Intel Corp., Folsom, CA).

Jason Wibbenmeyer                Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters, winter 2005 (initial employer: Ameren, St. Louis, MO).

Soumya Ramaswamy              High Speed 64-bit Thermometric Square-Root Carry Select Adder Based on the Chinese Abacus, winter 2005.

Rathod Snehal                        Architecture of Hybrid Signed-Digit Adder using carry-free property of redundant arithmetic and parallel redundant-to-binary converter, winter 2005.

Shailesh Radhakrishnan          A Low-Power 4-b 2.5 Gsample/s Flash Analog-to-Digital Converter Using QV Comparator and DCVSPG Encoder, fall 2004 (initial employer: Link Electronics, Cape Girardeau, Missouri).

Darren Schindel                      Arc Draw Algorithm Utilizing Bresenham Circle Algorithm and Multiple Clipping Techniques For Graphics Generation Using an Active Matrix Liquid Crystal Display, fall 2004  (initial employer: Unisys, Polymouth, MI.).

Kumar Yelamarthi                   Design Synthesis of Re-Convergent Manchester Carry Chain Adders, fall 2004 (continue for Ph.D. at WSU)

Nilesh Gunjal                           Design Synthesis of High-Speed Testable Hybrid Adders, fall 2004 (initial employer: Cingular Wireless, Dallas, TX.)

Pavan Lingamaneni                Low-Power Low-Leakage Asymmetric SRAM using Dual Threshold Voltages, summer 2004.

Mahesh Subramanian             Pipeline with Scan Insertion for Timing Driven Testable Convergent Tree Adders, summer 1999 (initial employer: Intel Corporation, San Jose, CA).

N. Thiagarajan                        VHDL Modeling, Simulation and Synthesis of Fully-Testable Fast Binary Carry-Save Multiplier without Final Addition, summer 1998 (initial employer: NEC America, Austin, TX).

Mahesh Wagh                          High-Level Design Synthesis with Redundancy Removal for High Speed Testable Binary Adders, summer 1998 (initial employer: Intel Corporation, Seattle, WA).

Khalil Habash                          VHDL Modeling, Simulation and Testing of a Fast Binary Adder with Conditional Carry Generator, summer 1997 (initial employer: Cray Research Corporation, Wisconsin).

Joaquin Romera                      Timing-Driven Testable VLSI Parallel Adders, summer1997 (initial employer: Intel Corporation, Portland, OR).

Rajesh Palamadai                   Implementation of Dynamic Huffman Coding Using CAM-Based CMOS VLSI Architecture, winter 1997 (initial employer: Mentor Graphics, Warren, NJ).

Sin Kwang Pok                        High Level Test Generation and Test Verification for the Enhanced Memory Chip (EMC), summer 1996 (initial employer: Baynacre, Union City, CA).

Anil Kempanna                       Cellular Automata Based Test Generator, winter 1995 (initial employer: Cadence Spectrum Design, San Diego, CA).

Anup Kumar                            Area-Time Optimal Digital Mixed CMOS/BiCMOS Parallel Adders, winter 1995  (initial employer: Credence Systems Corporation, Fremont, CA).

Chia-Lin Chan                         Efficient Methods for Partial Scan Sequential Circuit Design, fall 1994  (initial employer: Oak Technology, Sunnyvale, CA).

Tim Noh                                  VHDL Behavioral Fault Modeling and Fault Simulation System, April 1994  (initial employer: FORE Systems, Inc., Warrendale, PA).

Vijay K. Singh                         Circular Built-In Self-Test in VLSI Circuits, fall 1993  (initial employer: Advanced Micro Devices, Austin, TX).

Joel Yuen                                Concurrent Testing and VLSI Built-In Self-Test Design in Systolic Array Chip, fall 1992 (initial employer: Intel Corp., Chandler, AZ).

Ji-Der Lee                                Testability Enhancement and Hardware Partition for Testable Design, spring 1992.

Professional

Publications: 

2009-2016

  1. Benson, S. and Chen, C.-I. H., Lin, M. D. and Liou, L. L., “High Linear Chirp Receiver Using High Resolution Time-of-Arrival Estimation,” IEEE Transactions on Aerospace and Electronic Systems, 2016. Vol. 52, No. 3. pp. 1146-1154, June 2016.
  2. Lin, E., Chen, C.-I. H., Liou and Lin, L. L., D. M., “Detection and Sensitivity Analysis of Compressed Sensing Electronic RF Receiver,”  IEEE Radar Conference, pp. 1-6, Philadelphia PA, May 2016.
  3. Chen, J. and Chen, C.-I. H., “Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection,” VLSI Design Journal, Vol. 2015, Article ID 408035,, pp. 1-9, 2015.
  4. George, K. and Chen, C.-I. H., “Performance Measurement of a High-Performance Computing System Utilized for Electronic Medical Record Management,” International Journal of Advancements in Computing Technology, Vol. 7, No. 1, pp. 1-8, January 2015.
  5. Chen, J. and Chen, C.-I. H, “1-2 GHz Tuning Frequency Band Pass Filter with Controllable Pass Band and High Stopband Rejection, IEEE International Microwave Symposium, pp. 1-4, Phoenix, AZ, May 2015.
  6. George, K. and Chen, C.-I. H., “Multiple Signal Detection Digital Wideband Receiver Utilizing Hardware Accelerators,” IEEE Transactions on Aerospace and Electronic Systems, Vol. 49, No. 2, pp. 706-715, April 2013.
  7. George, K. and Chen, C.-I. H., “Measurement Setup and Performance Analysis of Digital Receiver System with Multiple Signal Detection and Expandable Bandwidth Capabilities on a Multi-Processor Hardware Platform,” International Journal of Engineering Sci. and Man., Vol. 3, No. 1, pp. 46-54, 2013.
  8. George, K. and Chen, C.-I. H., “Modular Test RF Instrumentation and Measurement for a Hybrid Computing Digital Wideband Receiver,” IEEE International Instrumentation and Measurement Technology Conference, pp. 352-356, May 2014.
  9. Boppana, V. K., S. Ren and Chen, C.-I. H., “Low Power and High Speed CPL-CSA Adder,” 2014 IEEE National Aerospace and Electronics Conference, Dayton, OH, July 2014.
  10. Liou, L. L., Lin, M. D., Lin, E. and Chen, C.-I. H., “Sensitivity Simulation of Compressed Sensing Based EW Receiver Using Orthogonal Matching Pursuit Algorithm,” IEEE National Aerospace and Electronics Conference, Dayton, OH, July 2014.
  11. Yelamarthi, Y. and Chen, C.-I. H., “Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations,” IEEE Transactions on Semiconductor Manufacturing, Vol. 25, No. 2, pp. 255-265, May 2012.
  12. George, K. and Chen, C.-I. H., “A Hybrid Computing Platform Digital Wideband Receiver Design Instrumentation and Performance Measurement,” IEEE Transactions on Instrumentation and Measurement, Vol. 60, No. 12, pp. 3956-3958, Dec. 2011.
  13.  George, K. and Chen, C.-I. H., “Biologically-Inspired Signal Processor Using Lateral Inhibition and Integrative Function Mechanisms for High Instantaneous Dynamic Range,” International Journal on Smart Sensing and Intelligent Systems, Vol. 4, No. 4, pp. 547-567, Dec. 2011.
  14. Benson, S. and Chen, C.-I. H., “Adaptive Thresholding for High Dual-Tone Signal Instantaneous Dynamic Range in Digital Wideband Receiver,” IEEE Transactions on Instrumentation and Measurement, Vol. 60, No. 5, pp. 1869-1875, May 2011.
  15. George, K. and Chen, C.-I. H., “Automated Mixed-Signal SoC BIST Synthesis utilizing Hardware Accelerators,” IEEE International Instrumentation and Measurement Technology Conference, May 2012.
  16.  Lin, M. D., Liou, L. L., Benson, S. and Chen, C.-I. H., “Mono-bit Digital Chirp Receiver using mono-bit IFM (Instantaneous Frequency Measurement) Receiver as a core”,  2011 IEEE National Aerospace and Electronics Conference, Dayton, OH, July 2011.
  17. Yelamarthi, Y. and Chen, C.-I. H., “A Timing Optimization Technique for Nanoscale CMOS Circuits Susceptible to Process Variations,”  IEEE International Instrumentation and Measurement Technology Conference, pp. 109-113, Hangzhou, China, May 2011.
  18. George, K. and Chen, C.-I. H., “Design and Performance Evaluation of a Digital Wideband Receiver on a Hybrid Computing Platform,”  IEEE International Instrumentation and Measurement Technology Conference, Hangzhou, China, May 2011.
  19. Yelamarthi, Y. and Chen, C.-I. H., “Delay Optimization Considering Power Saving in Dynamic CMOS Circuits,”  IEEE/ACM International Symposium on Quality Electronic Design, pp. 364-369, Santa Clara, CA, March 2011.
  20. Yelamarthi, Y. and Chen, C.-I. H., “Dynamic CMOS Load Balancing and Path Oriented In Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations,” VLSI Design Journal, Vol. 2010, Article ID 230783, pp. 1-13, 2010.
  21.  Lee, Y.-H. G. and Chen, C.-I. H., “Dynamic Kernel Function Fast Fourier Transform with Variable Truncation Scheme for Wideband Coarse Frequency Detection,” IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 5, pp. 1495-1504, May 2009.
  22.  George, K. and Chen, C.-I. H., “Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip,” IEEE Transactions on Instrumentation and Measurement, Vol. 58, No. 5, pp. 1555-1562, May 2009.
  23.  Yelamarthi, Y. and Chen, C.-I. H., “Process-Variation Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic,” IEEE Transactions on Semiconductor Manufacturing, Vol. 22, No, 1, pp. 31-39, 2009.
  24. Benson, S. and Chen, C.-I. H., “Adaptive Thresholding for High Dual-Tone Signal Instantaneous Dynamic Range in Digital Wideband Receiver,”  IEEE International Instrumentation and Measurement Technology Conference, pp. 616-619, Austin, Texas, May 2010.
  25.  Lee, Y.-H. G. and Chen, C.-I. H., “Fixed-Point Fixed-Precision Dynamic Kernel Function FFT Processor for Wideband Signal Detection,”  IEEE International Instrumentation and Measurement Technology Conference, pp. 397-401, Austin, Texas, May 2010.
  26. Lee, Y.-H. G. and Chen, C.-I. H., “Bit-Precision and Performance Analysis of Dynamic Kernel Function Fast Fourier Transform,”  IEEE International Instrumentation and Measurement Technology Conference, pp. 187-191, Austin, Texas, May 2010.
  27. Lee, Y.-H. G. and Chen, C.-I. H., “Dual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme",  IEEE International Symposium on Circuits and Systems, pp. 920-923, Taipei, Taiwan, May 2009.
Professional Affiliations/Memberships: 

Editorial Board                                                                                              Service

Integration, the VLSI Journal                                                                               Associate Editor

VLSI Design Journal                                                                                            Editor

Awards/Recognition: 

Harrell V. Noble Award, IEEE Dayton Section, 2016

 

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