Weisong Wang, Ph.D.
Dr. Wang specializes in microelectronics based on WBG and UWBG materials, 3D hetergeneous integration, semiconductor manufacturing, and micro-electro-mechanical systems (MEMS) research.
Curriculum Vitae
Research Interests
While Intel is investing $20 billion to build a factory in Ohio to host “Intel 18A” process and CHIPS and Science ACT is signed recently by the President, it’s time to join the exciting research of microelectronic devices! This is a three-year project at AFRL. Tuition and stipend will be fully covered. Yearly stipend increase is guaranteed. To qualify this project, the student must be a U.S. citizen and could be a newly started graduate student or an undergraduate student who’s in 4+1 program or interested in pursuing graduate degree next Fall. If you are interested in this opportunity, please contact with Dr. Weisong Wang, weisong.wang@wright.edu
Currently funded research projects:
•“Dielectric integration in ultra-wide band gap transistors for high temperature applications”, AFRL Regional Network - Midwest, $200,000, 9/2024-8/2026
•“Electronic-grade dielectric integration for high-power and high frequency electronic devices”, Defense Associated Graduate Student Innovators (DAGSI) funded by Ohio Department of Higher Education, $117,881, 8/2024-8/2026
•“Integration of AlScN-based dielectric in high-power GaN-based radio frequency transistors”, Air Force Research Lab, ~$140,000 (continuous renewal), 2/2022-8/2025
Project description:
Successful integration of dielectrics into a transistor process flow with negligible defect density has historically been the key for wide scale application of electronic devices. Dielectrics are needed not only as gate insulators for operation of metal oxide semiconductor field-effect transistors (MOSFETs), they are also needed for passivation of metal semiconductor FET (MESFET) and high-electron mobility transistors (HEMT; which is a different form of MESFET). This research targets successful integration of dielectrics in high-power GaN-based RF transistors. This will require optimization of a wide range of process parameters during device fabrication in AFRL/RY’s class 100 (ISO-5) cleanroom. Resultant devices will go through extensive electrical (C-V, I-V, transient, noise), optical (different forms of spectroscopy and microscopy) and materials characterization for confirming the effect of different process parameters on device performance.